Marvell to sample 192.4Tbps switch silicon

The Teralynx T100 was architected to deliver the lowest power consumption and lowest latency at this bandwidth.

With switching and networking components consuming approximately 15-25% of total rack power, low-power switch silicon is a strategic necessity.

The chip enables flatter, higher-radix fabrics optimized for demanding AI workloads by reducing the number of AI network tiers and optical links.

High-radix, high-bandwidth low-latency switches are key to increasing GPU utilization, lowering tail latencies and improving convergence times for training algorithms, and the T100 bandwidth efficiency while lowering overall rack power consumption and improving cluster

For scale-out deployments, the T100 supports up to a 512-port radix, enabling operators to consolidate network tiers, simplify architectures and reduce latency across large AI training clusters with tens of thousands of accelerators.

For scale-up deployments, the device’s pipeline architecture supports a variety of interconnect standards and emerging scale-up fabric protocols—including the Ethernet Scale-Up Networking (ESUN) protocol—as well as the latest Ultra Ethernet Consortium (UEC) requirements.

The chip comes in ball grid array (BGA), co-packaged copper (CPC) and co-packaged optics (CPO) implementations

It  delivers latency-optimized topologies, integrated telemetry, AI-native congestion control and proprietary traffic management logic required by advanced datacentre architectures.

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