FRAM scaled to 22nm | Electronics Weekly

FRAM has been scaled to the 22nm manufacturing node using an innovative 3D capacitor architecture.

By vertically integrating ferroelectric capacitors made from hafnium zirconium oxide (HZO) thin films, CEA-Leti researchers achieved memory cells that are 2.5 times smaller than standard SRAM matching the density of SRAM at the 10nm node.

“This 3D ferroelectric capacitor-based FRAM technology enables high-speed, high-density, low-voltage operation of non-volatile memory arrays,” said Simon Martin, lead author of the paper, “Engineering 3D HZO Ferroelectric Capacitors to Scale Down 22nm Embedded FeRAM.”

Previously the capacitor determined the cell footprint. To overcome this physical limit, the researchers shifted to a vertical architecture, building the capacitor upwards rather than outwards.

The team demonstrated two back-end-of-line (BEOL) integration schemes for 3D ferroelectric capacitors (FeCaps) at 22nm, utilizing advanced patterning and deposition techniques.

Array functionality with Gaussian bit distributions was confirmed down to 0.047 μm² 1T-1C FRAM bitcells operating at just 1.3V, featuring a standard logic selector and a 3D FeCap with an aspect ratio of roughly 4:1.

The researchers also demonstrated a clear path to even greater density: 3D FeCaps with an aspect ratio of 17:1, a 60nm diameter, and a 120nm pitch—shrinking the capacitor footprint to just 0.0028 μm².

A higher aspect ratio maximizes the effective surface area of the ferroelectric capacitor within each bitcell, enlarging the memory window without sacrificing array density.

The high-aspect-ratio 3D capacitors exhibited wake-up-free behaviour consistent with an approximately 80 percent orthorhombic phase fraction in the HZO film, as confirmed by precession electron diffraction (PED)..

CEA-Leti plans to integrate the demonstrated high-aspect-ratio ferroelectric capacitors into dense FRAM arrays on a 22nm FDSOI platform, aiming to achieve the highest-performance embedded FeRAM to date.