Universal Chiplet Interconnect Express and Design Verification

The Universal Chiplet Interconnect Express (UCIe) is a standard die-to-die protocol from the UCIe Consortium. It’s one of the popular interfaces for connecting chiplets together. I talked with Mayank Bhatnagar, Product Marketing Director at Cadence, about UCIe and how Cadence is supporting chip development (watch the video above). 

One of the tools available to designers is the Cadence Verification IP (VIP) for UCIe (see figure). The IP is designed for integration at the IP, system-on-chip (SoC), and system level. VIP for UCIe can run on any simulator that supports SystemVerilog utilizing the Universal Verification Methodology (UVM).

Verification engineers are able to check UCIe features at each functional layer, including the PHY, D2D, and protocol level. The VIP for UCIe can be used as a standalone stack or layered options like the PCI Express (PCIe) VIP.