On-Package Chiplet Innovations with UCIe

Chiplets have changed the way high-performance processors, GPUs, and artificial-intelligence (AI) accelerators are built. High bandwidth memory (HBM) is just one type of chiplet, but it makes a significant difference in chip performance by providing very wide, very fast memory interfaces for compute engines that demand more accelerated memories.

Dr. Debendra Das Sharma, Intel Senior Fellow and Chair of the UCIe Consortium, gave this keynote presentation at the 2026 Chiplet Summit. By definition, chiplets need to be connected together to form a useful chip. One way to do this is via Universal Chiplet Interconnect Express (UCIe). Chiplets are needed to address a range of issues, including the reticle limit that’s hampering large die often required for GPUs and AI accelerators (Fig. 1).

The latest version is UCIe 3.0, which brings more functionality and faster transfer rates (Fig. 2). UCIe can now deliver up to 64 Gtransfers/s. These on-chip interconnects are faster and more efficient than off-chip connections, and multiple dies can be supported in a single chip package.

Using a standard like UCIe will allow designers to develop systems more quickly and make a chiplet marketplace practical, since connectivity is key to its success.