Clock Domain Crossing and Synchronizers (Part 2): Best Practices

The other dominant factor in the MTBF exponential term is the number of synchronizer stages (n). Increasing the number of flip-flop stages will increase the MTBF exponentially as well, but in turn, it will increase the area, leakage power, and number of cycles after which the data can be sampled safely.

Sometimes the available synchronizers may not meet the required MTBF specifications. In other situations, they may not have enough stages, or the PDK may not have synchronizer cells at all. In that case, it will be necessary to instantiate, connect, and pre-map the flip-flops, to form a multi-stage synchronizer with the required configuration and specs.

Ultimately, it’s key to eliminate any stage delay tpd that might arise due to the placing and connecting of the pre-mapped flip-flops. This will directly affect the T_r given by Equation 2, impacting the overall MTBF exponentially.

When placing a pre-mapped multi-stage synchronizer, engineers must ensure that the flip-flops are placed closely together to decrease any wire delay as much as possible. They also must make sure that no buffers or inverters are placed between them.

Under normal circumstances, the flip-flops are to be placed closely together, directly connected to each other with no logic in between. However, the place-and-route (PnR) tool may encounter hold violations and start inserting buffers between the synchronizer’s flops. These hold violations are bogus and can be misleading. The system is already in a metastable state and the flip-flops with their current configuration are trying to resolve it.

That’s not a normal timing path with a stable 1 or 0 trying to get latched to the flip-flop and violates hold. On the contrary, this increases the stage delay tpd and decreases the time the flip-flops have to resolve the metastability T_r.

To avoid that, a false path constraint can be applied between the flip-flops. It will prevent any modification or optimization the tool might perform on these paths. Disable timing constraint shouldn’t be used instead of false path. This signal is crossing to a different domain and has an infinite arrival time window, which can cause crosstalk and induce noise violations. The tool should take this into consideration.

Using Synchronizers to Reduce the Risk of Metastability

There are several best practices for engineers to maximize the MTBF of synchronizers and minimize the risk of metastability:

• Use low-voltage threshold flip-flops synchronizers with small setup and aperture time.
• Use multiple flip-flop stages to improve signal integrity.
• In case of pre-mapping a flip-flop synchronizer, it’s necessary to:
  • Place the flip-flop stages as close as possible to each other.
  • Prevent the tool from placing any buffers in between the flip-flop stages.