Imec and EV Group demo fine-pitch wafer-to-wafer hybrid bonding

In addition, a record high Cu pad alignment accuracy was achieved, leveraging EVG’s most advanced wafer bonding equipment. Imec and EVG intend to further advance the wafer-to-wafer hybrid bonding roadmap, in support of logic-to-logic and memory-to-logic tier stacking use cases that require an extremely high level of interconnect density – as envisioned in imec’s CMOS 2.0 scaling paradigm.

Future compute system architectures designed around imec’s CMOS 2.0 scaling paradigm are driving the wafer-to-wafer hybrid bonding roadmap toward 200nm interconnect pitch. With CMOS 2.0, a system-on-chip (SoC) is partitioned into heterogeneous, functional tiers that are reconnected using 3D interconnect technologies. Depending on the application, CMOS 2.0 envisions splitting the logic part of the SoC into a high-drive logic layer and a high-density logic layer.

This logic-to-logic tier stacking requires extremely high interconnect densities, which can only be offered by the most advanced wafer-to-wafer hybrid bonding technology.

Imec now demonstrates a robust wafer-to-wafer hybrid bonding technology at 200nm interconnect pitch, obtained on a test vehicle with four layers of routable interconnects pre-processed on each of the wafers prior to bonding.

In addition, a Cu pad-to-pad post-bond overlay vector below 40nm was obtained for 100% of the dies over the full 300mm wafer – a world first. EVG’s cutting-edge hybrid and fusion wafer bonding system, the GEMINI FB, was essential for achieving this unprecedented overlay accuracy – critical for ensuring a high electrical yield.

“This breakthrough fine-pitch hybrid bonding result was achieved by co-optimizing all the critical elements of imec’s hybrid bonding process flow,” says Imec’s Zsolt Tokei “these include, among others, the use of SiCN as the dielectric material (as pioneered by imec) and a chemical mechanical polishing (CMP) step prior to bonding. The latter was optimized for high across-wafer uniformity to produce extremely flat dielectric surfaces while achieving a controlled few nanometers of recess for the Cu pads. The high overlay accuracy and control, enabled by EVG’s wafer bonding tool, were additionally facilitated by an improved Cu pad design and by pre-bond lithography corrections.”

“We continue to advance our hybrid wafer bonding flow and drive the roadmap well below 200nm interconnect pitch to unlock the most demanding logic-to-logic and memory-to-logic stacking use cases,” adds Zsolt Tokei. “This will require even more enhanced overlay performance, which we intend to further explore in collaboration with EVG”.