Pairing SiC MOSFETS and gate drivers

The Studio helps engineers by analysing device combinations and recommending well-matched SiC MOSFET and gate driver pairings based on their system requirements

An online  tool accelerates development by enabling evaluation of device‑level switching behavior, losses, and trade‑offs early in the design process, reducing iteration before advancing to full system‑level analysis

An interactive, personalised simulation environment gives engineers visibility into timing, waveform behaviour, and trade‑offs behind each recommended pairing

As power electronics grow more complex, engineers must carefully match gate drivers with switching devices to achieve optimal efficiency, minimize losses, and ensure safe operating temperatures.

Early component selection decisions have a direct impact on these system-level outcomes, particularly as teams balance competing requirements. Traditionally, this process requires time-consuming manual evaluation and simulation via extensive datasheet comparisons, spreadsheet analysis, and empirical testing.

The Studio simplifies this challenge by guiding engineers through a step-by-step process to identify the ideal combination of an onsemi gate driver and SiC MOSFET based on their requirements. Well-matched pairings can be compared quickly, helping reduce iterations and refine power architectures earlier in the development process. This reduces design risk, shortens time to market, and helps ensure systems perform as intended in real-world conditions.

The cloud-based environment gives engineers access to a private and secure workspace on onsemi.com where they can use an intuitive workflow to explore device combinations based on their inputs. The tool evaluates a wide range of gate driver combinations with the selected SiC MOSFET, using transparent methods based on established industry equations and real-world performance calculations. The evaluation logic is clear and inspectable for users.

Through the  Studio, engineers can examine key figures of merit for each pairing, including:

• Switching timings
• Gate voltage and current (V/I) waveforms
• Voltage overshoot margins relative to device ratings
• Switching energy losses, such as turn‑on and turn‑off energy

These insights allow engineers to compare pairing trade‑offs relevant to their application and gain early visibility into factors that influence electromagnetic interference behavior and reliability margins. Results are visualized through an interactive waveform viewer, enabling more informed pairing decisions before designs are advanced into full system‑level simulation. Additional onsemi technologies will be added to the Elite Pairing Studio in the future.

By providing well-matched pairings of SiC MOSFETs and gate drivers tailored to application needs, the onsemi  Studio enables earlier design decisions with a clearer understanding of switching behavior and trade-offs.

Those pairing insights can then be carried forward using Studio-generated PLECS system‑level simulation models and evaluated in the onsemi Elite Power Simulator to fine‑tune efficiency, thermal, and loss performance.

Together, this development path helps designers translate early pairing insights into improved system‑level efficiency and performance for demanding applications including AI data centers, electric vehicles, industrial systems, and electrification infrastructure.

The onsemi Elite Pairing Studio is available now through the onsemi website.

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