New NOC Ties Together FPGA SoC

Altera announced the Agilex 2X family (Fig. 1) that includes the high end Agilex 27 that will be available first. Developers can scale up from the low power, low cost Agilex 22. All incorporate Altera’s third generation HyperFlex FPGA fabric.

The Agilex 27 targets high performance applications from analyzing radar information to implementing machine learning models to processing network data streams. The new HyperFlex fabric delivers a 1.8x performance/W improvement over the earlier Agilex family. The fabric is surrounded by the HyperFlow Data Network network-on-chip (NOC) that ties it to all the major data components on the chip from memory controllers to the CPU complex.

The Agilex 27 CPU complex includes Arm Cortex-A720 and Cortex-A520 cores. This is a step up from the prior FPGA SoC generation. Developers can also include Nios V soft cores in their design. This is a configurable RISC-V core. Versions can support operating systems like Linux as well as real-time systems like FreeRTOS.

The Agilex 27’s serial interface support includes transceivers that will deliver up to 256 Gb/s of throughput including hard core interfaces to support 1.6 T and 800 G Ethernet as well as PCIe 7.0 and CXL.

While the Agilex 27 has the usual high speed GPIO and crypto support, it is the UCIe support that will be interesting to watch in the future. It will be the basis for Direct RF solutions in the future that incorporate analog-to-digital converters (ADC) and digital-to-analog converters (DAC) in a chiplet-based implementation. In theory, UCIe support would also make it easier to link to third party IP or provide off-chip UCIe support.

The Agilex 2x family is supported by Altera’s Quartus Prime development suite. This includes the Visual Designer Studio. The suite has been enhanced with the Quartus IQ AI Expert Companion that bring agentic AI to the FPGA developer’s workflow (Fig. 3).

The Companion uses FPGA-specific knowledge along with project context to take advantage of Quartus skills and agentic workflow support. It can deliver faster timing closures by prioritizing steps across compilation, timing and verification. The AI support has shown timing closure improvements of 10x and overall design cycle improvements of 1.5x.

Overall, the Agilex 2x and QuartusIQ combine to allow developers to deliver higher performance FPGA SoC solutions faster and easier.