Apple M5 Pro and M5 Max Debut New “M-Core” Tier and SoIC 2.5D Packaging

Apple today launched its most advanced silicon design yet with the introduction of the M5 Pro and M5 Max processors for MacBook Pro laptops. These new SoCs feature an 18-core CPU with six new “super cores” and 12 performance cores. The main difference between the M5 Pro and M5 Max lies in the size of the integrated GPU and the maximum memory capacity that Apple can equip these SoCs with. With these two SoCs, Apple has added another core tier to its lineup. In the M5 Pro/Max SoCs, a new tier called “M-core” has been introduced, which sits between the Super Core and Efficiency Core. What used to be performance and efficiency cores in the regular M5 have been renamed. Essentially, Apple renamed the performance core to super core and introduced an M-core tier that sits between the super core and efficiency core. Interestingly, the efficiency core is completely absent from the new SoCs, resulting in a combination of performance and middle-class cores, which will enhance the performance of these processors. In this context, the regular M5 SoC has four super cores and six efficiency cores.

Inside these new SoCs, the six super cores run at 4.61 GHz, while the M-cores run at 4.38 GHz. The M-core is a 7-wide out-of-order execution CPU that has roughly 70% of the P-core performance with slightly lower power usage. This new core tier is expected to boost the multithreaded performance of the M5 Pro/Max processors by up to 20%, according to some preliminary estimates found on Chinese Baidu forums. For the M5 Pro, Apple has included 16 MB of cache for the super cores, 16 MB of cache for the M-cores, and 24 MB of memory cache. The memory choice is LPDDR5X, which runs at 9,600 MT/s and offers up to 64 GB of capacity. In the M5 Max, the core cache remains the same, but the memory cache is increased to 48 MB, and the memory capacity is upgraded to a configuration of up to 128 GB. Both SoCs feature GPU cores that run at 1.62 GHz, with the M5 Pro having a 20-core iGPU and the M5 Max having a 40-core iGPU.

One of the most interesting innovations is the use of TSMC’s SoIC-MH 2.5D, which marks Apple’s first true chiplet design. Previously, Apple’s “Ultra” SoCs were technically chiplet designs that simply bonded two dies together to create a single massive SoC. However, with the new SoIC-MH 2.5D technology from TSMC, Apple has separated the CPU/NPU from the GPU, moving away from the monolithic design era that limited scaling opportunities for M-series SoCs. Now, Apple can independently scale the size of the CPU clusters with more cores and scale the GPU die with many more cores. This allows for the creation of more SKUs without having to maintain the die size near the reticle limit of 830 mm², improving yield and saving Apple from dealing with the high number of defective dies that a large silicon area can cause.