1.4nm single-patterned processes need High NA, says imec

‘For A14 and A10 logic nodes, requirements for the most critical metal layers (i.e., M0 and M2) are very demanding,’ says imec, ‘lines/spaces with ≤20nm pitches, aggressive tip-to-tip (T2T) structures to interrupt the lines (T2Ts with ≤15nm CD and ≤3nm LCDU as an industry target), and random vias with ≤30nm center-to-center distances.’

‘0.33NA EUV lithography would require 3-4 masks to pattern these features, whereas 0.55NA EUV (High-NA) lithography can do this in one single exposure, as experimentally observed,’ says imec.

Imec could also overcome the challenges in achieving good T2T control: a target LCDU below 3nm could be realized for 13nm T2T structures by co-optimizing source, mask (using low n phase shift masks), resist and etch (using directional etch techniques) [7].

Figure 3 – (Left) While 0.33NA EUV lithography would require 4 masks to pattern metal A14/A10, (middle and right) High NA EUV lithography can print the same layout with only one mask.

DRAM roadmap: single patterning of D1d and D0a bitline peri / storage node landing pad layers

The ability to eliminate complex multi-patterning steps also makes High NA EUV lithography a roadmap enabler for future DRAM nodes, i.e., 32nm (D1d) and 28nm (D0a) DRAM, says imec.

For these nodes, experiments have confirmed the feasibility of using High NA EUV lithography to pattern the BLP/SNLP layer – the layer that contains the bitline periphery and storage node landing pads.

While 0.33NA EUV lithography requires at least three masks for patterning these BLP/SNLP layers, 0.55NA EUV lithography can accomplish the same task with only one mask.

Figure 4 – High NA EUV lithography as a roadmap enabler for next-gen DRAM: (top left) while 0.33NA EUV lithography requires multi-patterning for D1d/D0a, (top right) 0.55NA EUV lithography enables single-patterning of the BLP/SNLP layer. (Bottom) TEM cross sections of 0.33NA and 0.55NA enabled BLP/SNLP layers (ADI = after development inspection; AEI = after etch inspection.)