Simple Power Sequencing for Multi-Rail Processors

From graphics processor units (GPUs) and central processing units (CPUs) to field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and heterogeneous SoCs, every processor requires power sequencing. These digital loads often operate from multiple voltage rails, each of which may supply a different on-chip power domain. Power sequencing is the process of applying and removing power from these voltage rails in a specific order during system startup and shutdown.

If the appropriate sequencing isn’t followed, the function of the load may be limited and defective. Also, in extreme cases, the load can be destroyed. To prevent this, sequencing functions are employed.

This article discusses different possibilities for the implementation of a sequencing and voltage-monitoring function. It also introduces a new, simple-to-use sequencing solution that requires no programming, digital communication, or bias power supply. These features are important because the sequencer itself needs to be powered on first in a system. By that time, processors or other loads usually aren’t running yet.

How Power Sequencing Typically Works

One common approach to sequencing involves placing several DC-DC converters in front of the processor and switching them on one after the other by linking the generated voltages with enable (EN) pins. One drawback with this approach is the requirement of voltage regulators with an exact definition of the precision enable pin. The other drawback is that a fixed sequence of switch-off of the individual voltages is difficult to implement. Also, the exact time course can only be implemented with additional cumbersome circuitry.