AMD Details Upcoming Zen 6 PQOS Extensions: Advanced Bandwidth and Privilege Controls

Imagine you’re a web hosting vendor leasing out specific number of CPU cores of a large core-count processor. You’d want to specify QoS limits on the shared L3 cache performance for those cores, so they don’t hamper performance of other tenants. AMD this week released a technical document detailing the Platform Quality of Service (PQOS) ISA extensions for its next-generation Zen 6 microarchitecture. These ISA enhancements provide sysadmins and cloud providers with greater control over processor and memory subsystem performance. The latest document outlines three primary additions to the Zen 6 PQOS feature set, Global Bandwidth Enforcement (GLBE), Global Slow Bandwidth Enforcement (GLSBE), and Privilege-Level Zero Association (PLZA). These features are designed to scale performance management across complex multicore environments by allowing software to regulate bandwidth and execution privileges more effectively across expansive groups of logical processors. The development shows that AMD is steering toward a more closely collaborative hardware QoS solution for its multicore processors.

A highlight of the Zen 6 PQOS updates is the implementation of Global Bandwidth Enforcement (GLBE), which allows system software to specify L3 external bandwidth limits for groups of cores that span across multiple traditional QoS Domains. By grouping these into a unified “GLBE Control Domain,” AMD enables a competitively shared bandwidth ceiling for specific Classes of Service (CoS). This upgrades older architectures that only provided L3 external bandwidth enforcement on a strictly per-domain granularity. Next up, AMD introduced Global Slow Bandwidth Enforcement (GLSBE), a parallel feature that applies the exact same multi-domain bandwidth limiting principles to system memory explicitly designated as “Slow Memory.” Both GLBE and GLSBE provide granular controls via specific model-specific registers.

Rounding out the Zen 6 microarchitecture updates is Privilege-Level Zero Association (PLZA), a unique performance and security monitoring feature that grants hardware the ability to automatically associate highly privileged execution with a specific CoS or Resource Monitoring Identifier (RMID). Historically, AMD PQOS mechanisms tied these identifiers to each logical processor on a standard per-thread basis. PLZA, however, empowers the system to actively override this thread-level association whenever a logical processor executes at Privilege Level Zero (CPL=0). This ensures that system software, such as the host OS kernel or a hypervisor running with AMD SVM enabled can utilize tailored resource limits regardless of the thread’s standard user-level configuration.